The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode disposed overlying a semiconductor substrate and spaced apart source and drain regions disposed within the substrate and between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel within the substrate between the source and drain regions.
It is well known that the performance of a transistor device can be improved by applying an appropriate stress to the channel region to enhance the mobility of majority carriers. For example, the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor can be increased by applying a tensile longitudinal stress to the channel. Similarly, the mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor, can be increased by applying a compressive longitudinal channel stress. Tensile and compressive stress liner films have been incorporated as channel stress-inducing layers for both NMOS and PMOS devices, respectively, for the 65 nm, 45 nm, and 32 nm technology nodes. However, because the thickness of these films decreases with device pitch, the stress applied, and thus the performance benefit achieved, also declines with each new technology generation.
Accordingly, it is desirable to provide methods for fabricating MOS devices having highly stressed channels. Further, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.